Semiconductor memory arrays are used extensively in today's digital and computer systems. These memory arrays are mainly used in such systems for storing data and computer programs or instructions which manipulate data to perform specific functions. Some semiconductor memory arrays are volatile; that is, they lose their memory content in response to its source power being cut-off. These volatile semiconductor memory arrays include, for example, static random access memory (SRAM) and dynamic random access memory (DRAM). Other semiconductor memory arrays are non-volatile; that is, they do not lose their memory content in response to its source power being cut-off. These non-volatile memory include, for example, electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash EEPROM, and others.
Referring initially to FIG. 1, a schematic diagram of typical prior art example of a semiconductor memory array 10 is shown, along with associated circuitry for addressing and performing memory operations. The semiconductor memory array 10 typically comprises a plurality of field effect transistors structurally arranged in an array consisting of rows and columns of transistors. Generally, each transistor in a memory array stores a particular bit of data, and accordingly, the transistors are generally referred to as memory cells. In the typical configuration, the transistors or memory cells forming a column of the semiconductor memory array 10 have their drains electrically connected to each other by a conductive line; typically referred to as the "bitline" or "BL", for short. Also in the typical configuration, the transistors or memory cells forming a row of the semiconductor memory array 10 have their gates connected to each other by another conductive line; typically referred to as the "wordline" or "WL", for short. In some semiconductor memory arrays, all of the transistors or memory cells in the memory array 10 have their sources connected to each other, forming a common source. It is conventional that the drains and sources of the memory cell transistors are interchangeable.
As shown in FIG. 1, the semiconductor memory array 10 contains "m" rows of transistors or memory cells, wherein the variable "i" represents the i'th row. The "i" and "m" variables will also be used in conjunction with "WL" to designate the wordlines connecting in common the gates of the i'th and m'th rows of transistors or cells, respectively. The semiconductor memory array 10 also contains "n" columns of transistors or memory cells wherein the variable "j" represents the j'th column. The "j" and "n" variables will also be used in conjunction with "BL" to designate the bit-lines connecting in common the drains of the j'th and m'th column of transistors or memory cells, respectively. Using these designations, a particular transistor or memory cell in the memory cell can be designated as C(row, column), wherein C(i, j) is the transistor or memory cell in the i'th row and the j'th column.
Typically, a particular transistor or memory cell in the semiconductor memory array 10 is addressed using a row address decoder 12 and a column address decoder 14. The outputs of the row address decoder 12 are coupled to corresponding wordlines (WLI-WLM) of the memory array 10. The row address decoder 12 receives a row address for selecting a particular row of transistors or memory cells for which the desired transistor or cell to be addressed is in. If the semiconductor memory array 10 is comprised of N-type transistors, then the row address decoder 12 produces a logical "high" on the selected wordline. Similarly, outputs of the column address decoder/Y-multiplexer (Y-mux) 14 are coupled to corresponding bit-lines (BLI-BLN) of the memory array 10. The column address decoder 14 receives a column address for selecting a particular column of transistors or memory cells for which the desired transistor or memory cell to be addressed is in. The column address decoder/Y-mux select a bitline to be interfaced or connected to the sense amplifier 16 or the input buffer 20.
By placing logical "highs" on the selected wordline and appropriate bias voltage on the selected bit-line of the selected transistor or memory cell, and more specifically, on the gate and drain of the selected transistor, a determination of whether the cell contains a logical "1" or a logical "0" can be determined by measuring the drain current, designated herein as I.sub.D. A sense amplifier 16 is included for sensing the drain current I.sub.D. The sense amplifier 16 measures the drain current ID by sensing the voltage at its input, and in particular, the difference in its input voltage between the sensing of a logical "0" and a logical "1". This difference in its input voltage is usually termed the "sense window" and can be designated as .DELTA.V. Therefore, by having the sense amplifier 16 sense its input voltage, the data content of the selected transistor or memory cell can be determined. Output and input buffers 18 and 20 are provided for buffering the data as it is transferred and received.
Because of the recent trend of densifying memory circuits, that is, increasing the content memory size for a given integrated circuit size, semiconductor memory arrays, such as the one shown in FIG. 1, have grown to include a substantial amount of transistors or memory cells. Due to this increase in the semiconductor memory array, the performance and reliability of the memory array has been adversely affected. Specifically, with respect to the performance aspect of the memory array, the memory operation or read access time has increased with the increase in the number of transistors or memory cells of the semiconductor memory array of the type shown in FIG. 1. With respect to performance, the write disturbance or transistor voltage stress is now unnecessarily affecting more transistors or memory cells of the semiconductor memory array of the type shown in FIG. 1, which adversely affects the operational lifetime of the semiconductor memory array.
Specifically, the increase in the read access time of the semiconductor memory array 10 has occurred because more transistors or memory cells in a column of the memory array are coupled to the sense amplifier 16. The read access time, which can be represented as .DELTA.T, is proportional to the sense window voltage .DELTA.V, the capacitance C.sub.SA as seen at the input of the sense amplifier 16, and inversely proportional to the read drain/source current ID During a read operation, the column address decoder 14 couples the selected bit-line to the sensing input of the sense amplifier 16, and in particular, couples the drain of each column transistor or memory cell to the sensing input of the sensing amplifier. Because each transistor of the semiconductor memory array has a Parasitic junction capacitance C.sub.J associated with its drain, the increase in the memory array size has resulted in an increase in the capacitance C.sub.SA at the sensing amplifier input. Because the read access time is proportional to the capacitance C.sub.SA, the increase in the number of column transistors has resulted in an increase in the read access time.
For example, the prior art semiconductor memory array 10 of FIG. 1 includes "m" transistors or memory cells within each column. Assuming that each transistor has a Parasitic junction capacitance C.sub.J associated with its drain, then the capacitance contribution from a column of transistors to the input capacitance C.sub.SA of the sensing amplifier 16 is given by mC.sub.J. If the number of transistors or memory cells in semiconductor memory arrays continues to grow, as it is the trend today, and consequently, the number of column transistors grow (that is, "m" gets larger), then the capacitance contribution from a column of transistors or memory cells mC.sub.j also gets larger, which results in a large capacitance C.sub.SA seen at the input of the sense amplifier 16. The read access time, being proportional to the capacitance C.sub.SA, will also be larger. Thereby, slowing the speed in which the semiconductor memory array can be operated.
From a reliability standpoint, the more denser a semiconductor memory array gets, the more transistors or memory cells of the memory array are unnecessarily exposed to memory operation voltages. Specifically, during a write operation on the semiconductor memory array, which includes programming and erasing operations, a voltage typically around 5 to more than 12 Volts (depending on the type of semiconductor memory array) is applied to the drain of the transistors or memory cells of the memory array by way of the bit-lines. This means that each transistor or memory cell in a column of the memory array will be exposed to such voltage. This applied voltage causes stress of each selected column transistor or memory cell which degrades the operational lifetime of the transistor or memory cell. It also makes each of the column transistors susceptible to program disturbance; that is, their data content may be altered by the applied voltage.
Again, taking the example of the prior art semiconductor memory array of FIG. 1, it includes "m" transistors or memory cells per column of the array. During the write operation, a voltage typically around 5 to 12 Volts is applied to a bit-line of the memory array. This results in "m" column transistors or memory cells being exposed to such applied voltage. Since during the write operation only one transistor is accessed at a time for writing data thereto, a total of m-l transistors are unnecessarily exposed to the applied voltage. Again, as semiconductor memory arrays get denser, the number of column transistors "m" get larger; which results in more transistors (i.e. m-1) being unnecessarily exposed to the applied voltage. This has the adverse effects of degrading the operational lifetime of the transistors and making them susceptible to program disturbance.
The adverse effects of program disturbance and operational lifetime degradation is more prevalent in semiconductor memory array that uses the common source for performing writing operations. During the writing operation of this type of memory array, a voltage typically ranging from 5 to 12 volts (depending on the type of the semiconductor memory array) is applied to the common source. This results in all transistors or memory cells of the memory array being exposed to such applied source voltage, which degrades the operational lifetime of memory array and makes all transistors or memory cells therein susceptible to write disturbance.
For the source-voltage writing type of semiconductor memory arrays, the adverse effects are worse since more transistors or memory cells are unnecessarily exposed to the applied voltage. Taking the example of the prior art semiconductor memory array 10 of FIG. 1, it comprises an n.times.m array of transistors or memory cells all having a common source. Since during writing operation only one transistor will be accessed for writing data thereto, this means that a total of (n.times.m)-1 transistors or memory cells are unnecessarily exposed to such applied source voltage. Because of the trend to increase both n and m in today's design of semiconductor memory arrays, more transistors or memory cells will be unnecessarily exposed to such applied source voltage, which results in the proliferation of the operational lifetime degradation and program disturbance effects.
Thus, there is a need for a semiconductor memory array and associated memory operation circuit that meets today's expectation of providing more transistors or memory cells within a given die size, and provides improved read access time (i.e. improved performance) and reduces the negative effects of operational lifetime degradation and program disturbance (i.e. improved reliability).